Algoritmo de criptografia AES em hardware, utilizando Dispositivos de Lógica Programável (FPGA) e linguagem de Descrição de hardware (VHDL)

Abstract

The communication, of the most varied forms and ways, was always constant in human existence, as thought by many specialists like a basic necessity for the survival and existence of man. With the evolution of the communication form, the spoken to the written way and at present, for the telecommunication systems and computers, man felt the necessity and the importance of secrecy, for the realization of determined operations of sending and receiving information. Being so the process of communicating or sending respected secret information started to have special attention by humanity. Seeing that encoded information reports exist from the time of the Pharaohs and the Roman emperors, nowadays, with the advent of the new technologies, the cryptography became a basic tool for transferring of electronic information safer. This work presents the algorithm of cryptography AES (Advanced Encryption Standard), called algorithm of symmetrical cryptography, which was ratified and certified by the NIST (National Institute of Standards and Technology), government organ of the United States of America, like new standard of information encoding to be used in operations of commerce, technology of the information and security for electronic data. This work was developed using hardware description language (VHDL) and applied in device of programmable logic (FPGA) with the intention of obtaining a system of great speed and capacity of processing. His functioning will be presented, besides implementations of some functional blocks of the algorithm, with the obtained results in a device of the manufacturer ALTERA ®.